A phase-locked-loop clock generation system for a digital integrated circuit typically receives a reference frequency, and divides the reference frequency by a first constant to provide a first input to a phase detector. A local oscillator signal is divided by a second constant to provide a second input to the phase detector; an output of the phase detector controls frequency of the local oscillator. The local oscillator signal is then divided to provide a clock signal for the digital integrated circuit.
The counters of a clock frequency synthesis subsystem for a digital integrated circuit are often among the fastest switching devices of the circuit; flexibility in divide ratios of the counters in the phase-locked loop is often desirable since this permits locking to a greater range of reference frequencies while potentially permitting slower operation of the local oscillator.